Design of a Decimation Filter for Novel Sigma-delta Modulator

The steps involved in the design of decimation filter for high-resolution sigma-delta (ΣΔ) A/D converter are described. The design of a decimation filter is proposed that employs three stage – one Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This approach eliminates the need for multiplication, requires a maximum clock frequency equal to the sampling. Specifications of decimation filter are dependent upon the overall specification from ΣΔ A/D converter with sampling frequency 16 MHz. The design implements a decimation ratio of 64, allows a maximum resolution of 14 bits in the output of the filter. Values of quantize coefficients are obtained using the tool Matlab. The decimation filter deign is written in VHDL, using “topdown” design methodology. The verification is made with test vectors generated in VHDL test bench module. Finally, it explains how to implement design in Xilinx Spartan-3 FPGA.